Integrated circuits (ICs) are usually designed by creating an IC specification that describes the functions of the IC device. The design is thereafter reduced to a hardware description language (HDL), such as Verilog or VHDL, at a level of abstraction known as the registered transfer level (RTL). The HDL code functionally describes operations that the IC device will perform on data as they flow between circuit inputs, outputs and clocked registers. The HDL code is both machine and human readable and is commonly used for development, verification, synthesis and testing of integrated circuit designs.
During development, testing is performed on the HDL description of the IC device using a hardware simulator executing the HDL description of the IC design. Signals are supplied to the IC design to perform design functions under various conditions. To facilitate testing of IC designs that are controlled by IC firmware, there is a class of software tools, herein referred to as “co-verification tools”, that executes the IC firmware on a standard workstation. The IC firmware, which, during development, is usually written in a high level language such as C/C++, is compiled and executed on the workstation using the co-verification tool. As used herein, “firmware” comprises the code that operates the IC device so that the IC device can perform its functions. For example, IC firmware includes firmware residing on the IC device as well as software and firmware used by a CPU coupled to the IC device to execute IC functions.
The co-verification tool operates on the designer's workstation to operate the hardware simulation of the IC design to perform many of the same functions as the IC device (when fabricated) will perform when is coupled to its intended CPU. Using the co-verification tool, the workstation provides signals in a standard format (i.e., compatible to the industry or proprietary standard of the CPU interface) and supplies them to the IC design via a functional model of the processor or CPU bus in the hardware simulator, to thereby operate the IC design. Hence, the co-verification tool is used to verify both the IC design functions as well as the IC firmware.
One feature of the co-verification software tool is that the IC firmware is executed on the workstation. Consequently, it is not necessary to operate the IC firmware on a hardware simulation of the CPU, and therefore it is not necessary to simulate the CPU hardware. Elimination of the simulation of the CPU hardware simplifies the design process and verification for the IC device. Moreover, because the co-verification tool permits execution of the IC firmware on the workstation, it is not necessary to simulate the IC firmware for execution on the workstation.
One such co-verification tool, known as a “Virtual CPU” or “V-CPU”, is commercially available from Summit Design of West Marlboro, Mass.
It is often necessary to test the IC design during the design process with stimuli supplied through the IC's system interface that will be used for coupling the IC to peripheral and control devices. Examples of system interfaces include small computer systems interface (SCSI) and fibre channels. (Although these couplings are called “buses”, they may be serial or parallel buses and consist of single or plural data paths.) In the past, the test stimuli were generated by the hardware simulator in the form of test signals to the IC design through the system interface of the IC design. Responses to test stimuli were analyzed using the hardware simulator.
Prior to the present invention, the IC design was operated through the co-verification tool using the IC firmware and tested by the hardware simulator with test stimuli supplied through the system interface. Consequently, it was necessary to simulate the peripheral device and system interfaces, including firmware associated with the peripheral device, on the hardware simulator. Moreover, it was necessary to operate the hardware simulator to supply test stimuli to the IC design, and it was necessary that responses to the stimuli were analyzed on the hardware simulator. As a result, the flexibility permitted by workstations, including the use of software debug tools resident on workstations, was not available for testing the IC design. As a result, the test procedure through the system bus was both time consuming and limited. There is a need, therefore, for a technique that permits use of the workstation and its compatible programming languages for generating test stimuli to IC designs under test.